1. Field of the Invention
The present invention relates to a MOS transistor circuit having an operating speed compensation function.
2. Description of the Related Art
In recent years, an importance of reduction in a signal delay caused due to the wiring resistance and the wiring capacitance of the signal line is rising, with the miniaturization and the higher integration of LSI. In particular, it is an important design theme that a variation of a delay time of the clock signal (clock skew) used to synchronize the internal operations over the whole LSI (referred simply to as a “clock” hereinafter) should be reduced.
As the technology to reduce the clock skew, there is the method of constituting a clock tree. The “clock tree” is a tree-like clock supply route built up by utilizing a clock repeater (repeater buffer), and is designed such that wiring lengths from a clock supply source to an end flip-flop, and the like are set equal respectively. In the prior art, as set forth in JP-A-2002-7500, a variation of a clock delay is minimized by making the loads driven by the clock buffer equal and devising a geometrical shape of the clock tree (i.e., by the layout design technology).
In recent years, with the progress of the high driving performance and the high integration of the digital circuit, a power consumed in the semiconductor integrated circuit is increased correspondingly. Thus, a “voltage drop of the power supply” due to the resistance of the power supply wiring and a “temperature rise of the substrate” due to the current flowing through the resistor becomes an issue. The “voltage drop of the power supply” is such a phenomenon that the voltage at a power-supply supply point of the transistor is lowered because the current flows through the power supply wiring.
As described above, even though the layout of the clock tree is properly designed, a difference arises in actual characteristics of the transistor elements due to the influence of the “voltage drop of the power supply” and the “temperature rise of the substrate”, and thus in some cases a malfunction of the circuit is caused.
Then, explanation will be made concretely hereinafter. The power supply wirings have the resistance equivalently. For this reason, when a wiring length is prolonged, the resistance between the power supply voltage and the MOS transistor is increased proportionally, and thus the power supply potential supplied to the source of the PMOS transistor is reduced lower than the power supply potential (VDD) in design by the voltage drop by this resistance (IR-DROP). Also, a potential of the VSS wiring ground is lifted up by the voltage drop generated by the current flowing through the VSS wiring (ground) and an equivalent resistance of the VSS wiring, so that a potential supplied to the source of the NMOS transistor is increased higher than the VSS potential in design.
As a result of this, an operating speed of the MOS transistor circuit (the CMOS circuit) is lowered. That is, because the current flows through the power supply wiring, the voltage at the power-supply supply point of the transistor is lowered and also the operating speed of the transistor is lowered. Then, the voltage drop of the power supply is increased in the portion far from the power supply pad which is located on the outer periphery of the semiconductor integrated circuit, especially in the center portion of the semiconductor integrated circuit, while voltage drop of the power supply is decreased in the location that comes closer to the outer peripheral portion. Therefore, such a problem arises that a level of the power supply voltage drop becomes different according to the position (location) in the semiconductor integrated circuit device and also the characteristic of the MOS transistor become different (is varied) according to the position in the semiconductor integrated circuit device.
Also, the “temperature rise of the substrate” is such a phenomenon that the temperature of the substrate is locally increased by the heat generated by circuit operations. When the power consumption becomes larger, a heating value becomes larger and then the substrate temperature around such circuit rises. That is, a local rise of the substrate temperature is affected depending on where the highly driven circuit is placed. Therefore, such a phenomenon occurs that the substrate temperature is different according to the position (location) in the LSI. In other words, the operating speed of the MOS transistor (in the case of the digital circuit, a switching speed) has dependence on the power supply voltage and the ambient temperature, and a current capability of the MOS transistor is lowered as the power supply voltage becomes lower and the temperature becomes higher. Since a reduction of the current capability of the MOS transistor means a reduction of the switching speed, consequently the delay of each MOS transistor becomes different in response to the circuit position in the semiconductor chip and the operating situation of the circuit.
Therefore, as set forth in JP-A-2002-7500, even when the route lengths of the clock supply routes are made equal by rendering the loads uniform or devising the geometrical shape of the circuit, a large clock skew is generated when an amount of delay is changed in a part of MOS transistors. That is, it is concluded that, under the conditions that the power supply voltage is not dropped and the temperature is kept constant, even when amounts of delay of respective clock routes are kept equal, if a drop of the power supply voltage or a local rise of the substrate temperature is caused, a difference is generated in the characteristics of individual MOS transistors on the semiconductor chip, amounts of delay in respective clock routes are varied, the clock skew is increased, and a malfunction of the LSI may be caused in the worst case. In the prior art, no countermeasure against the variation of the circuit characteristics caused due to the different level of the voltage drop of the power supply and the increase of the substrate temperature according to the position in the semiconductor integrated circuit device is taken.